OpenRisc-6-wishbone实验
引言
学习和研究OR，wishbone是绕不开的问题。本小节就做一个简单的实验，进一步加深对wishbone总线的理解。
6.1 总线timing
请参考官方spec，链接如下：
http://opencores.org/opencores,wishbone
6.2 实验内容
一个master，一个slave，master通过wishbone传递数据（两个操作数）给slave，slave做加法运算，将结果传给master。
如图：
6.3 用modelsim emulate 结果，可以看到1 + 2 = 3
6.4 实验code,写blog的编辑器xheditor真是无语了。这个实验的5个.v文件都是分开的，但是这个编辑器非要弄到一起，人工还修改不了。
1>master
//`include "wb_conbus_defines.v"`timescale 1ns / 10psmodule my_master_model(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);inputack, err, rty;inputclk, rst;input[31:0]din;output[31:0]adr;output[31:0]dout;outputcyc, stb;output[3:0]sel;outputwe;//external registersreg [31:0] adr,dout;reg cyc,stb,we;reg [3:0] sel;//internal registersreg [31:0] result;initial begin adr=32'hffff_ffff; dout=32'hxxxx_xxxx; cyc=0; stb=0; sel=4'hx; we=1'hx; result=32'hxxxx_xxxx; #10; endtask write_numbers;input [31:0] slave_addr;input [31:0] operd_a,operd_b;begin @(posedge clk); adr=slave_addr; dout=operd_a; cyc=1; stb=1; we=1; @(posedge clk); while(~ack &~err)@(posedge clk); adr=slave_addr+32'h1; dout=operd_b; @(posedge clk); while(~ack &~err)@(posedge clk); @(posedge clk); @(posedge clk); adr=adr+32'h1; we=0; @(posedge clk); while(~ack &~err)@(posedge clk); result=din; cyc=0; stb=0; we=1'bx; adr=32'hxxxx_xxxx; dout=32'hxxxx_xxxx; endendtaskalways @(result,dout,adr)$display("master model time: %t dout:%h result:%h adr:%h ",$realtime,dout,result,adr);endmodule
2>slave
//`include "wb_conbus_defines.v"`timescale 1ns / 10psmodule my_slave_model(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); inputclk, rst;input[31:0]adr, din;output[31:0]dout;inputcyc, stb;input[3:0]sel;inputwe;outputack, err, rty;//output registersreg [31:0] dout;reg ack;//internal registersreg [31:0]Cal_A,Cal_B;reg [31:0] Result;reg A_Status,B_Status,R_Status;//reg Reslt_Enbl;//reg Oprd_Enbl;//reg Wrt_Continue;assign err=0;assign rty=0;always @(posedge clk)if(rst) begin A_Status<=0; B_Status<=0; Cal_A<=0; Cal_B<=0; endelse if(A_Status &B_Status) begin Result<=Cal_A+Cal_B; R_Status<=1'b1; A_Status<=0; B_Status<=0; endelse if(cyc & stb & we) begin if(adr==32'h10000000 & !A_Status) begin Cal_A<=din; A_Status<=1'b1; end else if(adr==32'h10000001 & !B_Status) begin Cal_B<=din; B_Status<=1'b1; end end /* always @(posedge clk) if(rst) begin Result<=0; Reslt_Enbl<=0; end else if(Oprd_Enbl) begin Result<=Cal_A+Cal_B; Reslt_Enbl<=1'b1; end */ always @(posedge clk) if(rst) dout<=0; else if(R_Status) begin dout<=Result; R_Status<=0; end always @(posedge clk) if(rst) begin ack<=0; end else if(stb & !ack) begin ack<=!ack; end else if(ack) ack<=0; always @(din,adr,stb,we,cyc,Cal_A,Cal_B,Result) $display("slave model time:%t din:%h adr:%h stb:%b we:%b cyc:%b operd_a: %h operd_b:%h result:%h",$realtime,din,adr,stb,we,cyc,Cal_A,Cal_B,Result); endmodule
3>bus top
///////////////////////////////////////////////////////////////////////// //////// WISHBONE Connection Bus Top Level //////// //////// //////// Author: Johny Chi //////// chisuhua@yahoo.com.cn //////// //////// //////// ///////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2000 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// Description//1. Up to 8 masters and 8 slaves share bus Wishbone connection//2. no priorty arbitor , 8 masters are processed in a round// robin way,//3. if WB_USE_TRISTATE was defined, the share bus is a tristate// bus, and use less logic resource.//4. wb_conbus was synthesis to XC2S100-5-PQ208 using synplify,// Max speed >60M , and 374 SLICE if using Multiplexor bus//or 150 SLICE if using tri-state bus.////`include "wb_conbus_defines.v"`timescale 1ns / 10ps`definedw 32// Data bus Width`defineaw 32// Address bus Width`definesw `dw / 8// Number of Select Lines`definembusw `aw + `sw + `dw +4 //address width + byte select width + dat width + cyc + we + stb +cab , input from master interface`definesbusw 3// ack + err + rty, input from slave interface`definemselectw 8// number of masters`definesselectw 8// number of slavers//`define WB_USE_TRISTATEmodule wb_conbus_top(clk_i, rst_i,// Master 0 Interfacem0_dat_i, m0_dat_o, m0_adr_i, m0_sel_i, m0_we_i, m0_cyc_i,m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, m0_cab_i,// Master 1 Interfacem1_dat_i, m1_dat_o, m1_adr_i, m1_sel_i, m1_we_i, m1_cyc_i,m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, m1_cab_i,// Master 2 Interfacem2_dat_i, m2_dat_o, m2_adr_i, m2_sel_i, m2_we_i, m2_cyc_i,m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, m2_cab_i,// Master 3 Interfacem3_dat_i, m3_dat_o, m3_adr_i, m3_sel_i, m3_we_i, m3_cyc_i,m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, m3_cab_i,// Master 4 Interfacem4_dat_i, m4_dat_o, m4_adr_i, m4_sel_i, m4_we_i, m4_cyc_i,m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, m4_cab_i,// Master 5 Interfacem5_dat_i, m5_dat_o, m5_adr_i, m5_sel_i, m5_we_i, m5_cyc_i,m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, m5_cab_i,// Master 6 Interfacem6_dat_i, m6_dat_o, m6_adr_i, m6_sel_i, m6_we_i, m6_cyc_i,m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, m6_cab_i,// Master 7 Interfacem7_dat_i, m7_dat_o, m7_adr_i, m7_sel_i, m7_we_i, m7_cyc_i,m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, m7_cab_i,// Slave 0 Interfaces0_dat_i, s0_dat_o, s0_adr_o, s0_sel_o, s0_we_o, s0_cyc_o,s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, s0_cab_o,// Slave 1 Interfaces1_dat_i, s1_dat_o, s1_adr_o, s1_sel_o, s1_we_o, s1_cyc_o,s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, s1_cab_o,// Slave 2 Interfaces2_dat_i, s2_dat_o, s2_adr_o, s2_sel_o, s2_we_o, s2_cyc_o,s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, s2_cab_o,// Slave 3 Interfaces3_dat_i, s3_dat_o, s3_adr_o, s3_sel_o, s3_we_o, s3_cyc_o,s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, s3_cab_o,// Slave 4 Interfaces4_dat_i, s4_dat_o, s4_adr_o, s4_sel_o, s4_we_o, s4_cyc_o,s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, s4_cab_o,// Slave 5 Interfaces5_dat_i, s5_dat_o, s5_adr_o, s5_sel_o, s5_we_o, s5_cyc_o,s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, s5_cab_o,// Slave 6 Interfaces6_dat_i, s6_dat_o, s6_adr_o, s6_sel_o, s6_we_o, s6_cyc_o,s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, s6_cab_o,// Slave 7 Interfaces7_dat_i, s7_dat_o, s7_adr_o, s7_sel_o, s7_we_o, s7_cyc_o,s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, s7_cab_o);//////////////////////////////////////////////////////////////////////// Module Parameters//parameters0_addr_w = 4 ;// slave 0 address decode widthparameters0_addr = 4'h0;// slave 0 addressparameters1_addr_w = 4 ;// slave 1 address decode widthparameters1_addr = 4'h1;// slave 1 address parameters27_addr_w = 8 ;// slave 2 to slave 7 address decode widthparameters2_addr = 8'h92;// slave 2 addressparameters3_addr = 8'h93;// slave 3 addressparameters4_addr = 8'h94;// slave 4 addressparameters5_addr = 8'h95;// slave 5 addressparameters6_addr = 8'h96;// slave 6 addressparameters7_addr = 8'h97;// slave 7 address//////////////////////////////////////////////////////////////////////// Module IOs//inputclk_i, rst_i;// Master 0 Interfaceinput[`dw-1:0]m0_dat_i;output[`dw-1:0]m0_dat_o;input[`aw-1:0]m0_adr_i;input[`sw-1:0]m0_sel_i;inputm0_we_i;inputm0_cyc_i;inputm0_stb_i;inputm0_cab_i;outputm0_ack_o;outputm0_err_o;outputm0_rty_o;// Master 1 Interfaceinput[`dw-1:0]m1_dat_i;output[`dw-1:0]m1_dat_o;input[`aw-1:0]m1_adr_i;input[`sw-1:0]m1_sel_i;inputm1_we_i;inputm1_cyc_i;inputm1_stb_i;inputm1_cab_i;outputm1_ack_o;outputm1_err_o;outputm1_rty_o;// Master 2 Interfaceinput[`dw-1:0]m2_dat_i;output[`dw-1:0]m2_dat_o;input[`aw-1:0]m2_adr_i;input[`sw-1:0]m2_sel_i;inputm2_we_i;inputm2_cyc_i;inputm2_stb_i;inputm2_cab_i;outputm2_ack_o;outputm2_err_o;outputm2_rty_o;// Master 3 Interfaceinput[`dw-1:0]m3_dat_i;output[`dw-1:0]m3_dat_o;input[`aw-1:0]m3_adr_i;input[`sw-1:0]m3_sel_i;inputm3_we_i;inputm3_cyc_i;inputm3_stb_i;inputm3_cab_i;outputm3_ack_o;outputm3_err_o;outputm3_rty_o;// Master 4 Interfaceinput[`dw-1:0]m4_dat_i;output[`dw-1:0]m4_dat_o;input[`aw-1:0]m4_adr_i;input[`sw-1:0]m4_sel_i;inputm4_we_i;inputm4_cyc_i;inputm4_stb_i;inputm4_cab_i;outputm4_ack_o;outputm4_err_o;outputm4_rty_o;// Master 5 Interfaceinput[`dw-1:0]m5_dat_i;output[`dw-1:0]m5_dat_o;input[`aw-1:0]m5_adr_i;input[`sw-1:0]m5_sel_i;inputm5_we_i;inputm5_cyc_i;inputm5_stb_i;inputm5_cab_i;outputm5_ack_o;outputm5_err_o;outputm5_rty_o;// Master 6 Interfaceinput[`dw-1:0]m6_dat_i;output[`dw-1:0]m6_dat_o;input[`aw-1:0]m6_adr_i;input[`sw-1:0]m6_sel_i;inputm6_we_i;inputm6_cyc_i;inputm6_stb_i;inputm6_cab_i;outputm6_ack_o;outputm6_err_o;outputm6_rty_o;// Master 7 Interfaceinput[`dw-1:0]m7_dat_i;output[`dw-1:0]m7_dat_o;input[`aw-1:0]m7_adr_i;input[`sw-1:0]m7_sel_i;inputm7_we_i;inputm7_cyc_i;inputm7_stb_i;inputm7_cab_i;outputm7_ack_o;outputm7_err_o;outputm7_rty_o;// Slave 0 Interfaceinput[`dw-1:0]s0_dat_i;output[`dw-1:0]s0_dat_o;output[`aw-1:0]s0_adr_o;output[`sw-1:0]s0_sel_o;outputs0_we_o;outputs0_cyc_o;outputs0_stb_o;outputs0_cab_o;inputs0_ack_i;inputs0_err_i;inputs0_rty_i;// Slave 1 Interfaceoutput[`aw-1:0]s1_adr_o;input[`dw-1:0]s1_dat_i;output[`dw-1:0]s1_dat_o;output[`sw-1:0]s1_sel_o;outputs1_we_o;outputs1_cyc_o;outputs1_stb_o;outputs1_cab_o;inputs1_ack_i;inputs1_err_i;inputs1_rty_i;// Slave 2 Interfaceinput[`dw-1:0]s2_dat_i;output[`dw-1:0]s2_dat_o;output[`aw-1:0]s2_adr_o;output[`sw-1:0]s2_sel_o;outputs2_we_o;outputs2_cyc_o;outputs2_stb_o;outputs2_cab_o;inputs2_ack_i;inputs2_err_i;inputs2_rty_i;// Slave 3 Interfaceinput[`dw-1:0]s3_dat_i;output[`dw-1:0]s3_dat_o;output[`aw-1:0]s3_adr_o;output[`sw-1:0]s3_sel_o;outputs3_we_o;outputs3_cyc_o;outputs3_stb_o;outputs3_cab_o;inputs3_ack_i;inputs3_err_i;inputs3_rty_i;// Slave 4 Interfaceinput[`dw-1:0]s4_dat_i;output[`dw-1:0]s4_dat_o;output[`aw-1:0]s4_adr_o;output[`sw-1:0]s4_sel_o;outputs4_we_o;outputs4_cyc_o;outputs4_stb_o;outputs4_cab_o;inputs4_ack_i;inputs4_err_i;inputs4_rty_i;// Slave 5 Interfaceinput[`dw-1:0]s5_dat_i;output[`dw-1:0]s5_dat_o;output[`aw-1:0]s5_adr_o;output[`sw-1:0]s5_sel_o;outputs5_we_o;outputs5_cyc_o;outputs5_stb_o;outputs5_cab_o;inputs5_ack_i;inputs5_err_i;inputs5_rty_i;// Slave 6 Interfaceinput[`dw-1:0]s6_dat_i;output[`dw-1:0]s6_dat_o;output[`aw-1:0]s6_adr_o;output[`sw-1:0]s6_sel_o;outputs6_we_o;outputs6_cyc_o;outputs6_stb_o;outputs6_cab_o;inputs6_ack_i;inputs6_err_i;inputs6_rty_i;// Slave 7 Interfaceinput[`dw-1:0]s7_dat_i;output[`dw-1:0]s7_dat_o;output[`aw-1:0]s7_adr_o;output[`sw-1:0]s7_sel_o;outputs7_we_o;outputs7_cyc_o;outputs7_stb_o;outputs7_cab_o;inputs7_ack_i;inputs7_err_i;inputs7_rty_i;//////////////////////////////////////////////////////////////////////// Local wires//wire[`mselectw -1:0]i_gnt_arb;wire[2:0]gnt;reg[`sselectw -1:0]i_ssel_dec;`ifdefWB_USE_TRISTATEwire[`mbusw -1:0]i_bus_m;`elsereg[`mbusw -1:0]i_bus_m;// internal share bus, master data and control to slave`endifwire[`dw -1:0]i_dat_s;// internal share bus , slave data to masterwire[`sbusw -1:0]i_bus_s;// internal share bus , slave control to master//////////////////////////////////////////////////////////////////////// Master output Interfaces//// master0assignm0_dat_o = i_dat_s;assign {m0_ack_o, m0_err_o, m0_rty_o} = i_bus_s & {3{i_gnt_arb[0]}};// master1assignm1_dat_o = i_dat_s;assign {m1_ack_o, m1_err_o, m1_rty_o} = i_bus_s & {3{i_gnt_arb[1]}};// master2assignm2_dat_o = i_dat_s;assign {m2_ack_o, m2_err_o, m2_rty_o} = i_bus_s & {3{i_gnt_arb[2]}};// master3assignm3_dat_o = i_dat_s;assign {m3_ack_o, m3_err_o, m3_rty_o} = i_bus_s & {3{i_gnt_arb[3]}};// master4assignm4_dat_o = i_dat_s;assign {m4_ack_o, m4_err_o, m4_rty_o} = i_bus_s & {3{i_gnt_arb[4]}};// master5assignm5_dat_o = i_dat_s;assign {m5_ack_o, m5_err_o, m5_rty_o} = i_bus_s & {3{i_gnt_arb[5]}};// master6assignm6_dat_o = i_dat_s;assign {m6_ack_o, m6_err_o, m6_rty_o} = i_bus_s & {3{i_gnt_arb[6]}};// master7assignm7_dat_o = i_dat_s;assign {m7_ack_o, m7_err_o, m7_rty_o} = i_bus_s & {3{i_gnt_arb[7]}};assign i_bus_s = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i , s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i , s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i };//////////////////////////////////Slave output interface//// slave0assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} = i_bus_m[`mbusw -1:1];assigns0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0]; // stb_o = cyc_i & stb_i & i_ssel_dec// slave1assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} = i_bus_m[`mbusw -1:1];assigns1_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[1];// slave2assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} = i_bus_m[`mbusw -1:1];assigns2_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[2];// slave3assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} = i_bus_m[`mbusw -1:1];assigns3_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[3];// slave4assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} = i_bus_m[`mbusw -1:1];assigns4_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[4];// slave5assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} = i_bus_m[`mbusw -1:1];assigns5_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[5];// slave6assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} = i_bus_m[`mbusw -1:1];assigns6_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[6];// slave7assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} = i_bus_m[`mbusw -1:1];assigns7_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[7];/////////////////////////////////////////Master and Slave input interface//`ifdefWB_USE_TRISTATE// input from master interfaceassigni_bus_m = i_gnt_arb[0] ? {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i, m0_stb_i} : 72'bz ;assigni_bus_m = i_gnt_arb[1] ? {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i,m1_cyc_i, m1_stb_i} : 72'bz ;assigni_bus_m = i_gnt_arb[2] ? {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i, m2_stb_i} : 72'bz ;assigni_bus_m = i_gnt_arb[3] ? {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i, m3_stb_i} : 72'bz ;assigni_bus_m = i_gnt_arb[4] ? {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i, m4_stb_i} : 72'bz ;assigni_bus_m = i_gnt_arb[5] ? {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i, m5_stb_i} : 72'bz ;assigni_bus_m = i_gnt_arb[6] ? {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i, m6_stb_i} : 72'bz ;assigni_bus_m = i_gnt_arb[7] ? {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i} : 72'bz ;// input from slave interfaceassign i_dat_s = i_ssel_dec[0] ? s0_dat_i: 32'bz;assign i_dat_s = i_ssel_dec[1] ? s1_dat_i: 32'bz;assign i_dat_s = i_ssel_dec[2] ? s2_dat_i: 32'bz;assign i_dat_s = i_ssel_dec[3] ? s3_dat_i: 32'bz;assign i_dat_s = i_ssel_dec[4] ? s4_dat_i: 32'bz;assign i_dat_s = i_ssel_dec[5] ? s5_dat_i: 32'bz;assign i_dat_s = i_ssel_dec[6] ? s6_dat_i: 32'bz;assign i_dat_s = i_ssel_dec[7] ? s7_dat_i: 32'bz;`elsealways @(gnt , m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i,m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i,m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i,m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i,m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i,m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i,m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i,m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i)case(gnt)3'h0:i_bus_m = {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};3'h1:i_bus_m = {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i};3'h2:i_bus_m = {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i};3'h3:i_bus_m = {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i};3'h4:i_bus_m = {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i};3'h5:i_bus_m = {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i};3'h6:i_bus_m = {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i};3'h7:i_bus_m = {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i};default:i_bus_m = 72'b0;//{m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};endcaseassigni_dat_s = i_ssel_dec[0] ? s0_dat_i : i_ssel_dec[1] ? s1_dat_i : i_ssel_dec[2] ? s2_dat_i : i_ssel_dec[3] ? s3_dat_i : i_ssel_dec[4] ? s4_dat_i : i_ssel_dec[5] ? s5_dat_i : i_ssel_dec[6] ? s6_dat_i : i_ssel_dec[7] ? s7_dat_i : {`dw{1'b0}}; `endif//// arbitor //assign i_gnt_arb[0] = (gnt == 3'd0);assign i_gnt_arb[1] = (gnt == 3'd1);assign i_gnt_arb[2] = (gnt == 3'd2);assign i_gnt_arb[3] = (gnt == 3'd3);assign i_gnt_arb[4] = (gnt == 3'd4);assign i_gnt_arb[5] = (gnt == 3'd5);assign i_gnt_arb[6] = (gnt == 3'd6);assign i_gnt_arb[7] = (gnt == 3'd7);wb_conbus_arbwb_conbus_arb(.clk(clk_i), .rst(rst_i),.req({m7_cyc_i,m6_cyc_i,m5_cyc_i,m4_cyc_i,m3_cyc_i,m2_cyc_i,m1_cyc_i,m0_cyc_i}),.gnt(gnt));//////////////////////////////////// address decode logic//wire [7:0]m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec;always @(gnt, m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec)case(gnt)3'h0: i_ssel_dec = m0_ssel_dec;3'h1: i_ssel_dec = m1_ssel_dec;3'h2: i_ssel_dec = m2_ssel_dec;3'h3: i_ssel_dec = m3_ssel_dec;3'h4: i_ssel_dec = m4_ssel_dec;3'h5: i_ssel_dec = m5_ssel_dec;3'h6: i_ssel_dec = m6_ssel_dec;3'h7: i_ssel_dec = m7_ssel_dec;default: i_ssel_dec = 7'b0;endcase////decode all master address before arbitor for running faster//assign m0_ssel_dec[0] = (m0_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m0_ssel_dec[1] = (m0_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m0_ssel_dec[2] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m0_ssel_dec[3] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m0_ssel_dec[4] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m0_ssel_dec[5] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m0_ssel_dec[6] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m0_ssel_dec[7] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);assign m1_ssel_dec[0] = (m1_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m1_ssel_dec[1] = (m1_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m1_ssel_dec[2] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m1_ssel_dec[3] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m1_ssel_dec[4] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m1_ssel_dec[5] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m1_ssel_dec[6] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m1_ssel_dec[7] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);assign m2_ssel_dec[0] = (m2_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m2_ssel_dec[1] = (m2_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m2_ssel_dec[2] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m2_ssel_dec[3] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m2_ssel_dec[4] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m2_ssel_dec[5] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m2_ssel_dec[6] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m2_ssel_dec[7] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);assign m3_ssel_dec[0] = (m3_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m3_ssel_dec[1] = (m3_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m3_ssel_dec[2] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m3_ssel_dec[3] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m3_ssel_dec[4] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m3_ssel_dec[5] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m3_ssel_dec[6] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m3_ssel_dec[7] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);assign m4_ssel_dec[0] = (m4_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m4_ssel_dec[1] = (m4_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m4_ssel_dec[2] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m4_ssel_dec[3] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m4_ssel_dec[4] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m4_ssel_dec[5] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m4_ssel_dec[6] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m4_ssel_dec[7] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);assign m5_ssel_dec[0] = (m5_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m5_ssel_dec[1] = (m5_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m5_ssel_dec[2] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m5_ssel_dec[3] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m5_ssel_dec[4] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m5_ssel_dec[5] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m5_ssel_dec[6] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m5_ssel_dec[7] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);assign m6_ssel_dec[0] = (m6_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m6_ssel_dec[1] = (m6_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m6_ssel_dec[2] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m6_ssel_dec[3] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m6_ssel_dec[4] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m6_ssel_dec[5] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m6_ssel_dec[6] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m6_ssel_dec[7] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);assign m7_ssel_dec[0] = (m7_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr);assign m7_ssel_dec[1] = (m7_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr);assign m7_ssel_dec[2] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr);assign m7_ssel_dec[3] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr);assign m7_ssel_dec[4] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr);assign m7_ssel_dec[5] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr);assign m7_ssel_dec[6] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr);assign m7_ssel_dec[7] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr);//assign i_ssel_dec[0] = (i_bus_m[`mbusw -1 : `mbusw - s0_addr_w ] == s0_addr);//assign i_ssel_dec[1] = (i_bus_m[`mbusw -1 : `mbusw - s1_addr_w ] == s1_addr);//assign i_ssel_dec[2] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s2_addr);//assign i_ssel_dec[3] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s3_addr);//assign i_ssel_dec[4] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s4_addr);//assign i_ssel_dec[5] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s5_addr);//assign i_ssel_dec[6] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s6_addr);//assign i_ssel_dec[7] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s7_addr);always @(m0_ssel_dec,s1_dat_o)$display("top model time: %t mo_ssel_dec: %b s1_data_in:%h",$realtime,m0_ssel_dec,s1_dat_o);endmodule//=====================================================================
4>bus arbiter
///////////////////////////////////////////////////////////////////////// //////// General Round Robin Arbiter //////// //////// //////// Author: Rudolf Usselmann //////// rudi@asics.ws //////// //////// //////// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //////// ///////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2000-2002 Rudolf Usselmann //////// www.asics.ws //////// rudi@asics.ws //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer.//////// //////// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //////// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //////// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //////// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //////// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //////// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //////// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //////// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //////// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //////// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //////// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //////// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //////// POSSIBILITY OF SUCH DAMAGE. //////// /////////////////////////////////////////////////////////////////////////////copy from wb_conmax////////// //`include "wb_conbus_defines.v"`timescale 1ns / 10psmodule wb_conbus_arb(clk, rst, req, gnt);inputclk;inputrst;input[7:0]req;// Req inputoutput[2:0]gnt; // Grant output//inputnext;// Next Target/////////////////////////////////////////////////////////////////////////// Parameters//parameter[2:0] grant0 = 3'h0, grant1 = 3'h1, grant2 = 3'h2, grant3 = 3'h3, grant4 = 3'h4, grant5 = 3'h5, grant6 = 3'h6, grant7 = 3'h7;/////////////////////////////////////////////////////////////////////////// Local Registers and Wires//reg [2:0]state, next_state;/////////////////////////////////////////////////////////////////////////// Misc Logic //assigngnt = state;always@(posedge clk or posedge rst)if(rst)state <= #1 grant0;elsestate <= #1 next_state;/////////////////////////////////////////////////////////////////////////// Next State Logic// - implements round robin arbitration algorithm// - switches grant if current req is dropped or next is asserted// - parks at last grant//always@(state or req ) beginnext_state = state;// Default Keep Statecase(state)// synopsys parallel_case full_case grant0:// if this req is dropped or next is asserted, check for other req'sif(!req[0] ) beginif(req[1])next_state = grant1;elseif(req[2])next_state = grant2;elseif(req[3])next_state = grant3;elseif(req[4])next_state = grant4;elseif(req[5])next_state = grant5;elseif(req[6])next_state = grant6;elseif(req[7])next_state = grant7; end grant1:// if this req is dropped or next is asserted, check for other req'sif(!req[1] ) beginif(req[2])next_state = grant2;elseif(req[3])next_state = grant3;elseif(req[4])next_state = grant4;elseif(req[5])next_state = grant5;elseif(req[6])next_state = grant6;elseif(req[7])next_state = grant7;elseif(req[0])next_state = grant0; end grant2:// if this req is dropped or next is asserted, check for other req'sif(!req[2] ) beginif(req[3])next_state = grant3;elseif(req[4])next_state = grant4;elseif(req[5])next_state = grant5;elseif(req[6])next_state = grant6;elseif(req[7])next_state = grant7;elseif(req[0])next_state = grant0;elseif(req[1])next_state = grant1; end grant3:// if this req is dropped or next is asserted, check for other req'sif(!req[3] ) beginif(req[4])next_state = grant4;elseif(req[5])next_state = grant5;elseif(req[6])next_state = grant6;elseif(req[7])next_state = grant7;elseif(req[0])next_state = grant0;elseif(req[1])next_state = grant1;elseif(req[2])next_state = grant2; end grant4:// if this req is dropped or next is asserted, check for other req'sif(!req[4] ) beginif(req[5])next_state = grant5;elseif(req[6])next_state = grant6;elseif(req[7])next_state = grant7;elseif(req[0])next_state = grant0;elseif(req[1])next_state = grant1;elseif(req[2])next_state = grant2;elseif(req[3])next_state = grant3; end grant5:// if this req is dropped or next is asserted, check for other req'sif(!req[5] ) beginif(req[6])next_state = grant6;elseif(req[7])next_state = grant7;elseif(req[0])next_state = grant0;elseif(req[1])next_state = grant1;elseif(req[2])next_state = grant2;elseif(req[3])next_state = grant3;elseif(req[4])next_state = grant4; end grant6:// if this req is dropped or next is asserted, check for other req'sif(!req[6] ) beginif(req[7])next_state = grant7;elseif(req[0])next_state = grant0;elseif(req[1])next_state = grant1;elseif(req[2])next_state = grant2;elseif(req[3])next_state = grant3;elseif(req[4])next_state = grant4;elseif(req[5])next_state = grant5; end grant7:// if this req is dropped or next is asserted, check for other req'sif(!req[7] ) beginif(req[0])next_state = grant0;elseif(req[1])next_state = grant1;elseif(req[2])next_state = grant2;elseif(req[3])next_state = grant3;elseif(req[4])next_state = grant4;elseif(req[5])next_state = grant5;elseif(req[6])next_state = grant6; endendcase endendmodule//==================================================================================================================
5>top
///////////////////////////////////////////////////////////////////////// //////// Top Level Test Bench //////// //////// //////// Author: Rudolf Usselmann //////// rudi@asics.ws //////// //////// //////// ///////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2000-2002 Rudolf Usselmann //////// www.asics.ws //////// rudi@asics.ws //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer.//////// //////// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //////// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //////// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //////// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //////// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //////// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //////// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //////// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //////// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //////// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //////// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //////// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //////// POSSIBILITY OF SUCH DAMAGE. //////// /////////////////////////////////////////////////////////////////////////////// rewrite from test the wb_conbus module//////`include "wb_conbus_defines.v"`timescale 1ns / 10psmodule tb_wb_conbus;regclk;regrst;// IO Prototypeswire[31:0]m0_data_i;wire[31:0]m0_data_o;wire[31:0]m0_addr_i;wire[3:0]m0_sel_i;wirem0_we_i;wirem0_cyc_i;wirem0_stb_i;wirem0_ack_o;wirem0_err_o;wirem0_rty_o;wire[31:0]s1_data_i;wire[31:0]s1_data_o;wire[31:0]s1_addr_o;wire[3:0]s1_sel_o;wires1_we_o;wires1_cyc_o;wires1_stb_o;wires1_ack_i;wires1_err_i;wires1_rty_i;// Test Bench Variablesreg[31:0]wd_cnt;integererror_cnt;integerverbose;// Misc Variables///////////////////////////////////////////////////////////////////////// Defines /////////////////////////////////////////////////////////////////////////// Simulation Initialization and Start up Section//initial begin$timeformat(-9, 1, " ns", 10);$display("\n\n");$display("*****************************************************");$display("* WISHBONE Connection Matrix Simulation started ... *");$display("*****************************************************");$display("\n");`ifdef WAVES $shm_open("waves");$shm_probe("AS",test,"AS");$display("INFO: Signal dump enabled ...\n\n");`endifwd_cnt = 0;error_cnt = 0; clk = 1; rst = 1;verbose = 1;/* repeat(5)@(posedge clk);s0.delay = 1;s1.delay = 1;s2.delay = 1;s3.delay = 1;s4.delay = 1;s5.delay = 1;s6.delay = 1;s7.delay = 1;*/#1; rst = 0; repeat(5)@(posedge clk);// HERE IS WHERE THE TEST CASES GO ...if(1)// Full Regression Run begin$display(" ......................................................");$display(" : :");$display(" : Regression Run ... :");$display(" :....................................................:");verbose = 0;//test_dp1;//test_rf;//test_arb1;//test_arb2;//test_dp2; m0.write_numbers(32'h1000_0000,32'h0000_0001,32'h0000_0002); endelseif(1)// Debug Tests begin$display(" ......................................................");$display(" : :");$display(" : Test Debug Testing ... :");$display(" :....................................................:");//test_dp2; endrepeat(1000)@(posedge clk);$finish;end// End of Initial///////////////////////////////////////////////////////////////////////// Clock Generation//always #5clk = ~clk;///////////////////////////////////////////////////////////////////////// Watchdog Counter//always @(posedge clk)if(m0_ack_o )wd_cnt = 0;elsewd_cnt = wd_cnt +1;always @(wd_cnt)if(wd_cnt > 5000000) begin$display("\n*******************************************");$display("*** ERROR: Watchdog Counter Expired ... ***");$display("*******************************************\n");$finish; end///////////////////////////////////////////////////////////////////////// IO Monitors/////////////////////////////////////////////////////////////////////////// WISHBONE Inter Connect//wb_conbus_top#(4,4'h0,4,4'h1,4,4'h2,4'h3,4'h4,4'h5,4'h6,4'h7)conbus(.clk_i(clk),.rst_i(rst),.m0_dat_i(m0_data_i),.m0_dat_o(m0_data_o),.m0_adr_i(m0_addr_i),.m0_sel_i(m0_sel_i),.m0_we_i(m0_we_i),.m0_cyc_i(m0_cyc_i),.m0_stb_i(m0_stb_i),.m0_ack_o(m0_ack_o),.m0_err_o(m0_err_o),.m0_rty_o(m0_rty_o), .s1_dat_i(s1_data_i),.s1_dat_o(s1_data_o),.s1_adr_o(s1_addr_o),.s1_sel_o(s1_sel_o),.s1_we_o(s1_we_o),.s1_cyc_o(s1_cyc_o),.s1_stb_o(s1_stb_o),.s1_ack_i(s1_ack_i),.s1_err_i(s1_err_i),.s1_rty_i(s1_rty_i) );///////////////////////////////////////////////////////////////////////// WISHBONE Master Models//my_master_modelm0(.clk(clk),.rst(rst),.adr(m0_addr_i),.din(m0_data_o),.dout(m0_data_i),.cyc(m0_cyc_i),.stb(m0_stb_i),.sel(m0_sel_i),.we(m0_we_i),.ack(m0_ack_o),.err(m0_err_o),.rty(m0_rty_o));///////////////////////////////////////////////////////////////////////// WISHBONE Slave Models//my_slave_model s1(.clk(clk),.rst(rst),.adr(s1_addr_o),.din(s1_data_o),.dout(s1_data_i),.cyc(s1_cyc_o),.stb(s1_stb_o),.sel(s1_sel_o),.we(s1_we_o),.ack(s1_ack_i),.err(s1_err_i),.rty(s1_rty_i));//`include "tests.v"endmodule