Tiny210 U-BOOT(十)----DDR2初始化顺序
现在网上的S5PV210的u-boot源码中关于内存的初始化过程，基本上我没有找到任何资料有过分析DDR2的内存初始化代码的。在看u-boot的这段代码时，也徘徊了很久，不知道如下手，很多文章或资料都将这一段分析过程有意无意的隐藏掉了，最多也只是提一下说参考裸板的代码，在找不到任何资料的情况下，我只能依靠芯片手册上，三星在内存控制器这一章，写的关于DDR2的初始化顺序的28个步骤来一条一条去读去看，在安静下来看了芯片手册以后，我发现三星给的裸板的DDR初始化代码和芯片手册上的初始化步骤完全一致，有的时候，最好的资料其实就在手边，只是我一直在想着找捷径，学习哪有那么多捷径？
现在开始关注一下芯片手册上关于DDR2的初始化流程，P598页：
1.查看芯片手册DDR2的初始化顺序
Initialization sequence for DDR2 memory type1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low. 2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_incbit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_onbit-field to ‘1’ to turn on the PHY DLL. 3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetcbit-fields to correct value according to clock frequency and memory tAC parameters. 4. Set the PhyControl0.ctrl_start bit-field to ‘1’. 5. Set the ConControl. At this moment, an auto refresh counter should be off. 6. Set the MemControl. At this moment, all power down modes should be off. 7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register. 8. Set the PrechConfigand PwrdnConfigregisters. 9. Set the TimingAref, TimingRow, TimingDataand TimingPower registers according to memory AC parameters. 10. If QoS scheme is required, set the QosControl0~15and QosConfig0~15registers. 11. Wait for thePhyStatus0.ctrl_lockedbit-fields to change to ‘1’. Check whether PHY DLL is locked. 12. PHY DLL compensates the changes of delay amountcaused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set thePhyControl0.ctrl_forcebit-field to correct value according to thePhyStatus0.ctrl_lock_value[9:2]bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL. 13. Confirm whether stable clock is issued minimum 200us after power on 14. Issue a NOPcommand using the DirectCmdregister to assert and to hold CKE to a logic high level.15. Wait for minimum 400ns. 16. Issue a PALL command using the DirectCmd register. 17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters. 18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters. 19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs. 20. Issue a MRS command using the DirectCmd register to reset the memory DLL. 21. Issue a PALL command using the DirectCmd register. 22. Issue two Auto Refreshcommands using the DirectCmd register. 23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL. 24. Wait for minimum 200 clock cycles. 25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters. 26. If there are two external memory chips, perform steps 14~25 for chip1 memory device. 27. Set the ConControlto turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.