gem5添加共享的L3cache，并将L2cache改为独立的
if options.l3cache:
if options.cpu_type == "arm_detailed":
system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
block_size=options.cacheline_size)
else:
system.l3 = L3Cache(size = options.l3_size, assoc = options.l3_assoc,
block_size=options.cacheline_size)
system.tol3bus = CoherentBus()
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
for i in xrange(options.num_cpus):
system.cpu[i].l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
block_size=options.cacheline_size)
system.cpu[i].tol2bus = CoherentBus()
system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
system.cpu[i].l2.mem_side = system.tol3bus.slave
for i in xrange(options.num_cpus):
if options.caches:
if options.cpu_type == "arm_detailed":
icache = O3_ARM_v7a_ICache(size = options.l1i_size,
assoc = options.l1i_assoc,
block_size=options.cacheline_size)
dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
assoc = options.l1d_assoc,
block_size=options.cacheline_size)
else:
icache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
block_size=options.cacheline_size)
dcache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc,
block_size=options.cacheline_size)
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
system.cpu[i].createInterruptController()
if options.l2cache:
system.cpu[i].connectAllPorts(system.cpu[i].tol2bus, system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
return system
