这个verilog程序怎么不能输出x
这个程序，我仿真时给的输入从65开始依次加一，可是输出不是x，而是按照输入为1开始依次加一的输出，就是输出为0，,1,16,15.......这是怎么回事啊
module CBP_INTER_table(clk,value,CBP_INTER);
input clk;
input [7:0] value;
output [7:0] CBP_INTER;
reg [7:0] CBP_INTER;
always @(posedge clk)
begin
case(value)
8'd1:
CBP_INTER <= 0;
8'd2:
CBP_INTER <= 19;
8'd3:
CBP_INTER <= 16;
8'd4:
CBP_INTER <= 15;
8'd5:
CBP_INTER <= 18;
8'd6:
CBP_INTER <= 11;
8'd7:
CBP_INTER <= 31;
8'd8:
CBP_INTER <= 13;
8'd9:
CBP_INTER <= 17;
8'd10:
CBP_INTER <= 30;
8'd11:
CBP_INTER <= 12;
8'd12:
CBP_INTER <= 9;
8'd13:
CBP_INTER <= 10;
8'd14:
CBP_INTER <= 7;
8'd15:
CBP_INTER <= 8;
8'd16:
CBP_INTER <= 1;
8'd17:
CBP_INTER <= 4;
8'd18:
CBP_INTER <= 42;
8'd19:
CBP_INTER <= 38;
8'd20:
CBP_INTER <= 27;
8'd21:
CBP_INTER <= 39;
8'd22:
CBP_INTER <= 33;
8'd23:
CBP_INTER <= 59;
8'd24:
CBP_INTER <= 26;
8'd25:
CBP_INTER <= 40;
8'd26:
CBP_INTER <= 58;
8'd27:
CBP_INTER <= 35;
8'd28:
CBP_INTER <= 25;
8'd29:
CBP_INTER <= 29;
8'd30:
CBP_INTER <= 24;
8'd31:
CBP_INTER <= 28;
8'd32:
CBP_INTER <= 3;
8'd33:
CBP_INTER <= 5;
8'd34:
CBP_INTER <= 51;
8'd35:
CBP_INTER <= 52;
8'd36:
CBP_INTER <= 37;
8'd37:
CBP_INTER <= 50;
8'd38:
CBP_INTER <= 43;
8'd39:
CBP_INTER <= 63;
8'd40:
CBP_INTER <= 44;
8'd41:
CBP_INTER <= 53;
8'd42:
CBP_INTER <= 62;
8'd43:
CBP_INTER <= 48;
8'd44:
CBP_INTER <= 47;
8'd45:
CBP_INTER <= 34;
8'd46:
CBP_INTER <= 45;
8'd47:
CBP_INTER <= 49;
8'd48:
CBP_INTER <= 6;
8'd49:
CBP_INTER <= 14;
8'd50:
CBP_INTER <= 55;
8'd51:
CBP_INTER <= 56;
8'd52:
CBP_INTER <= 36;
8'd53:
CBP_INTER <= 54;
8'd54:
CBP_INTER <= 41;
8'd55:
CBP_INTER <= 60;
8'd56:
CBP_INTER <= 21;
8'd57:
CBP_INTER <= 57;
8'd58:
CBP_INTER <= 61;
8'd59:
CBP_INTER <= 46;
8'd60:
CBP_INTER <= 22;
8'd61:
CBP_INTER <= 32;
8'd62:
CBP_INTER <= 20;
8'd63:
CBP_INTER <= 23;
8'd64:
CBP_INTER <= 2;
default:
CBP_INTER <= 8'bx;
endcase
end
endmodule
[解决办法]
是不是你顶层模块位宽跟下面的不一致，65是b1000001，如果你顶层位宽不对，就有可能变成b000001
