verilog--电平信号触发16进制计数器
怎么写由电平信号触发的十六进制计数器？即输入电平每改变一次，计数器增1。
。。。下面是小弟我写的，由两位电平输入信号触发的4位BCD计数器，但全编译后总生成组合循环，搞了两天。。。
module SimHex(Hhigh,Hlow,buffer,bufH,bufL);
input Hhigh,Hlow;
output reg[3:0] bufH,bufL;
output reg[7:0] buffer;
reg[3:0] D;
parameter f=4'b0000;
parameter t=4'b0001;
parameter HF=4'b1111;
always @(bufH or buffer) begin//high-bit counter in hexdecimal
case(bufH)
4'b0000:bufH<=4'b0001;
4'b0001:bufH<=4'b0010;
4'b0010:bufH<=4'b0011;
4'b0011:bufH<=4'b0100;
4'b0100:bufH<=4'b0101;
4'b0101:bufH<=4'b0110;
4'b0110:bufH<=4'b0111;
4'b0111:bufH<=4'b1000;
4'b1000:bufH<=4'b1001;
4'b1001:bufH<=4'b1010;
4'b1010:bufH<=4'b1011;
4'b1011:bufH<=4'b1100;
4'b1100:bufH<=4'b1101;
4'b1101:bufH<=4'b1110;
4'b1110:bufH<=4'b1111;
4'b1111:bufH<=4'b0000;
default:bufH<=4'b0000;
endcase
end
always @(buffer) begin//low-bit counter in hexdecimal
case(bufL)
4'b0000:bufL<=4'b0001;
4'b0001:bufL<=4'b0010;
4'b0010:bufL<=4'b0011;
4'b0011:bufL<=4'b0100;
4'b0100:bufL<=4'b0101;
4'b0101:bufL<=4'b0110;
4'b0110:bufL<=4'b0111;
4'b0111:bufL<=4'b1000;
4'b1000:bufL<=4'b1001;
4'b1001:bufL<=4'b1010;
4'b1010:bufL<=4'b1011;
4'b1011:bufL<=4'b1100;
4'b1100:bufL<=4'b1101;
4'b1101:bufL<=4'b1110;
4'b1110:bufL<=4'b1111;
4'b1111:bufL<=4'b0000;
default:bufL<=4'b0000;
endcase
end
always @(Hhigh or Hlow) begin
buffer<={bufH,bufL};
bufH<=buffer>>4;
bufL<=buffer;
end
endmodule
